MISDN v2 xhfc.ko

From mISDN.org

Contents 1 Cologne Chip AG's XHFC mISDN driver 2 using XHFC controllers in embedded systems 3 latest sources 4 using PCI bridge to access XHFC controller 5 interrupts, timing

Cologne Chip AG's XHFC mISDN driver

The XHFC driver demonstrates the access of the XHFC ISDN controller using the PCI2PI PCI bridge.

using XHFC controllers in embedded systems

the XHFC ISDN controller is designed to be used at embedded systems without the PCI2PI PCI bridge. The XHFC controller supports various processor interface modes, such as SPI for example. To use this XHFC layer1 driver without PCI2PI, you simply have to replace xhfc_pci2pi.[c,h] with your own processor interface implementation and re-implement the functions shown at the ASCII-art block diagram below. therefore, simply replace

#if BRIDGE == BRIDGE_PCI2PI
#include <linux/pci.h>
#include "xhfc_pci2pi.h"
#endif

with your own stuff.

latest sources

Filename   xhfc_su.c xhfc_su.h layer1 mISDN driver xhfc_pci2pi.c xhfc_pci2pi.h PCI Bridge 'PCI2PI' xhfc24sucd.h XHFC register definitions

using PCI bridge to access XHFC controller

                      +------ PCI2PI ---------+
                      |                       |
  +-----------+       |      write_xhfc()     |       +-----------------+
  | xhfc_su.c | ----> |      read_xhfc()      | ----> | XHFC controller |
  +-----------+       |      sread_xhfc()     |       +-----------------+
                      |  xhfc_register_pi()   |
                      |  xhfc_unregister_pi() |
                      +-----------------------+

The layer1 driver xhfc_su.c calls

• xhfc_register_pi() to initialize the bridge, which does all PCI register/hotplug-probing here
• xhfc_unregister_pi() to unregister bridge
• read_xhfc() to read an XHFC chip register
• write_xhfc() to write an XHFC chip register
• sread_xhfc() to read an XHFC chip ram based register using the so called short read method

interrupts, timing

The interrupt sources which are configured in the XHFC sample driver are used the following way:

• timer interrupt:
  • check if there is TX data to be sent and fill TX fifos to their max depth
  • read out the RX fifos fill state, if it is above threshold, read this data

• fifo interrupt:
  • at RX end-of-frame event: read all fifo data although the fill state is below threshold

• S/U interrupt
  • handle L1 state changes

The timer interrupt interval has to be fast enough to ensure that there are no RX FIFO overruns while the TX FIFOs cannot underrun when operating at full data rate. In other words: the minimum required interrupt interval depends on the FIFO depth.